China's information technology industry, China

The processor instruction set is sometimes referred to as machine instructions and the binary language _____ they are written is called machine language! You should not ___ the processor instruction set with the instructions ____ high-level programming languages, such as BASIC or PASCAL.

C. 1. a. by which b. at which c. in which d. which
A 1. confuse b. complicate c. mix d. puzzle
C 1. find out b. found out c. found in
1. explain the three empty option
2. translation
3. analysis of the sentence grammatical components (especially the first sentence … set is cometimes …. is called the machine lanuage! two is … how to explain?)

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August 2, 2011
dll (dynamic link library), there are two call measures implicit linking and explicit linking, implicit link through pragram comment (lib, “A.dll “)
# include” Ah “, the explicit link is through the Loadlibrary (_T (” A.dll “)); in the process necessary to call when dynamically loaded, but held dynamic load time sometimes some of the problems, the following is encountered in the test process to write a dll.
HINSTANCE m_hModel = LoadLibrary (_T (“DLL.dll”)); always return empty to through getlasterror (); get the return value of 126, meaning can not find the dll rely on components, when I feel unable to find this file in DLL.dll Later, I arrange the files to the working directory of the process calling this dll and then, so call the arrangement in the dll through another Bing extremely simplified I perceived, the contrast DLL.dll arrangements when less than this test process atl90.dll MFC90VD.dll msvcr90. Amazon electronic paper book dll msvcr90d.dll five documents, through the analogy targets held call arrangements for the property to find the problem
Description: held to write dll through the call process, the crossing getlasterror return value is always 126, through the correct wrong values ??http://www.cell- li.info/jiaru/635.html the Find
aware dll, it relies on the use of the dll can not find the dll project was arranged to still be able to handle the directory of the calling process
causes of http://www.btushop.info/gongsi/667.html:
arrangements for the dll never will rely on five documents (atl90 . dll MFC90VD.dll msvcr90.dll msvcr90d.dll) arranged to wince system above.
handling the measures:
any increase in the project properties (Properties) -> arrangements (Deployment) files (additional Files) in case of empty, or lack of these five one of the documents
then increase following
msvcr90.dll$ (BINDIR) / $ (INSTRUCTIONSET) / |% CSIDL_PR OGRAM_FILES% / $ (ProjectName)0
atl90.dll$ (BINDIR) / $ (INSTRUCTIONSET) / |% CSIDL_PROG RAM_FILES% / $ (ProjectName)0
msvcr90d.dll$ (BINDIR) / $ (INSTRUCTIONSET) / |% CSIDL_P ROGRAM_FILES% / $ (ProjectName)0
MFC90UD.dll$ (BINDIR) / $ (INSTRUCTIONSET) / |% CSIDL_PR OGRAM_FILES% / $ (ProjectName)0
then recompile http://www.okoneclick.info/lianxiwomen/589.html arrangements, meeting all the call and the caller as well as five files in the unified file folder be able to pass through
The process of review through the
Emulator therefore able to define the box data; he had to understand if inferred, then write the offensive to infer ; he had learned to a for loop, so know how to eliminate the filled one or more lines.
a site diagnostic reports
OC learning – class, early initialization, memory, discipline

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July 10, 2011
real chip manufacturers the core technology in the hands of Americans and Japanese
First, cpu parts, starting a set of data, the chip area: < br />
Orion 4210-118mm2,
a5,-110mm2,
tegra3-89mm2,
ti4430-69mm2,
tegra2-49mm2.
Orion chip area, Samsung shi soc ability not much stronger than Apple. Chip area the consequences of heat is not easy to control, so gs2 a lot of people in the reaction heat is too high is the truth. Even four core tegra3-are better than Orion. The ti4430 ranked third tegra2 chip of the smallest, and thus minimum heat.
just PM me say “the minimum number of transistors of the chip area is also at least, this is not necessarily
that is, of course, because the new generation of mobile phone chips are basically are GF or TSMC 45 nanometer manufacturing process, the minimum number of transistors of the chip area will at least, the required driving voltage is small, at least calorific natural, the HD2 Qualcomm 8250 with the 65-nm process transistors with fewer chips area than the above are still large, but that is the 2009 chip, 2011
32/30 nm / and later the 28-nanometer process used in the PC CPU / GPU and SSD controller chip and NAND flash memory, the performance requirements of these things is the machine urgent and endless (for example, the site server)
personal mobile phone chip is relatively not so urgent
fever reading to see the performance, normal speaking, the larger the chip area, the stronger performance. A few slices of processor cpu parts are purchased armv7 cortax A9-based authorization, so the cpu architecture is basically the same, the difference lies in the a tegra2 memory channel controller-bit wide, only 32bit, and castration neon acceleration module In some ways, such as the flash and video performance of the software solution is not strong. Several other CPUs have neon, memory bits wide for 64bit (dual-channel and single channel the difference is not large) (tegra3 or 32bit, but support ddr3 memory), and thus better support for flash and video. So, the solution flash experience, the quad-core with neon plus 3.1/2.4 system gpu hardware tegra3 of the strongest, Orion and ti4430 performance is not comparable. The video decoder is called Orion and ti4430 decoding neon decoding capabilities will not be much difference. So it comes last ti4430 and Orion experience is basically comparable to the same very smooth. However, the the ti4430 chip area than the Orion small too much. Heat than the Orion will be much better. So on the cpu the overall quality of ti4430 dual-core a9 which is the best, no one.
look at the gpu The ti4430 use sgx540 of the overclocked version, the original operating frequency upgrade from 200mhz to 300mhz, of course, the performance increase is not so exaggerated, and only about 50 percent, but stronger than gefoce ulp a. power vr gpu wins in the compatibility of the most exclusive games, in addition to nv, all of the game and ultimately, its packets. The gs2 mali400, even stronger than the performance of the overclocked version sgx540 about 50%, but the support of a single map format, and is not compatible with many mainstream effects, resulting in very poor compatibility, powerful performance but rather into heat, and become a burden. Gpu on ti4430 dual-core in the overall quality of the highest only to lose in four core tegra3.
Qualcomm 8260 integrated baseband chip, the package size of a surprisingly 196mm2. The CPU area is probably about the same size and TI4430. The same frequency of performance of the Scorpion core as cortax the A9 core and dual-core bus structure links, as well as every single individual 256K L2 cache (dual-core A9 unified shared 1M). In addition to the data stream processing (eg, connection speed) is slightly faster, and other aspects of the same dual-core A9 has a large gap, mainly reflected in the general. However, due to its integrated neon, the solution flash capacity, and tegra2 almost slightly stronger a little bit (smooth broadcast Youku HD). Video decoding capabilities, and tegra2 also similar, except that support hp 1080P mkv package format but the same weakness.
say the GPU part of this generation adreno220 performance is still very strong, but HTC pit father qHD resolution, resulting in the GPU when rendering to render 35% of the pixels, slow down the adreno220 performance test of the game, lost to 2X. However adreno220 after several generations of development, the compatibility or good. />

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outdated phone CPU:
the outdated phone Android phone on the market today use several categories of CPU and nothing more than the Samsung S5PC110 (below referred to as C110), Ti OMAP 3430 (36X0), Qualcomm, the Snapdragon 8X50 (MSM 7230/MSM 8225).
Ti OMAP 3430 (L1 64KB, L2, 256KB, support 256M DDR) is the industry first use of ARM7-instructionset (ARM7 instruction set), the CPU, Ti call it the Cortex A8 (Ti full ARM provide a framework, not modified, so the introduction of the speed of the product soon), because of a new architecture CPU, so performance is increased than previous ARM 11 architecture U is generally believed that the same frequency under ARM 7 performance of ARM 11 200% (By the way, Nokia current flagship is still about 600M ARM 11 architecture rotten U weakness, HTC early G1, G2, G3, which also uses the ARM 11 architecture CPU). It is because of the early launch of the OMAP 3430, so for now, has to keep up with the mainstream, ask to use MS shoes after the upgrade to Android 2.2 will know the problems encountered in play Flash, 3430CPU the highest support 256M, not Moto mean, not original to you on a 512M of RAM.
OMAP 36X0 (512M DDR2) and OMAP 3430 of the difference, is that the former uses the 45NM process, the latter with the 65NM process, both the architecture are the Cortex A8, and there is no difference. The advanced process is to bring the advantages of higher frequencies and smaller power consumption and heat. But when it comes frequencies have to say that the Ti and Moto is not kind, Milestone2 and Droid 2 OMAP 3630, the design frequency is 800M to 1G, and obstinately to overclocking selling Droid 2 International version of OMAP 3640 design frequency 1G, sell to overclocked to 1.2G. Although the CPU such products already exist room for overclocking, but do not sell according to the design frequency is always uncomfortable.
OMAP 3430 and OMAP behind 36X0 integrates the SGX 530 graphics core, but because of the Cortex A8 in 65NM times, and can not control the power consumption problem, the Ti at the same time to control the OMAP 3430 frequency, shameless the frequency of the SGX 530 also reduced (SGX 530 design frequency is 200Mhz OMAP 3430 inside the SGX 530 frequency is only 110Mhz), this is why the MS game to run, but one of the reasons for the 3GS, although both the CPU hardware architecture and specifications are similar. />

As for a good game of legendary MS, this is because the early games are all transplanted from the IPhone platform IPhone hardware platform is the PowerVR MBX-Lite (the IPhone 3G with 3GS of the SGX 530 the IPhone 4 of the SGX 535), accounting for a big and cheap. But with the introduction of Qualcomm CPU machines more and more, this advantage is more and more obvious (both core behind the contrast to say).
Then there is the Samsung C110 (45NM the L1 64KB, L2, 512KB, support 512M DDR2), this CPU is the most powerful CPU in the Cortex A8 architecture, one of the CPU Samsung home the i9000, and pass Meizu M9. The C110 also uses Cortex A8 architecture, just modify the arrangement of the chip inside the core, reducing the area (the architecture of Apple IPhone 4 with the A4 and C110, but it simplifies the unwanted components, in addition to the L2 cache to 640KB, improve performance and reduce power consumption).
In addition C110 integrates the SGX 540, and the wood castration DSP module, I9000 play 720P like the video is no pressure the Meizu predecessor is to do a multimedia same stress-free (home made hardware is good. cost savings, estimated Moto to castrate hardware modules are cost Incidentally, MS FM module Moto castration, the lack of switching circuit, so do not expect the MS can use FM). So next time do not Han MS performance to kill the i9000, the M9 like jokes, even the brother of MS Milestone2 encountered I9000 is also fall by the wayside.
The final step is to Pa of mobile communications and chip industry high-pass, so why call to tyrants, because the people holding the CDMA and WCDMA patents, as long as the production of the mobile phone manufacturers cell phone, you need to pay to Qualcomm fees (and even domestic Fudge extremely powerful TD-SCDMA, but also obediently to the high-pass pay). 8X50 snapdragon Qualcomm produced based on the ARM7 architecture, re-design of the CPU, the actual performance of the Cortex A8 of the same frequency slightly higher is generally believed that about 5%. And control its power consumption and heat well, 1G 8250 equivalent to 600M OMAP 3430, of course, because the re-designed to control the power available in the Snapdragon 8X50 than 3430 nights more than six months, led directly to the rivers and lakes appear on the 3430 ** family through the rumors (of course, this rumor is there are still a certain extent it exists). The reality is that Snapdragon 8X50 (65NM L1 64KB L2 640KB support 512M DDR) video decoder, built-in DSP support for 720P H.264 hardware solutions, other formats are not open codec is
also need soft decoding. However, because of high default frequency, so soft solution 480P like the video is no pressure. In addition the Snapdragon 8X50 integrated Adreno 200, but to Pa Qualcomm also did not give a codec, so game manufacturers optimization more difficult, but Qualcomm aware of this problem has been gradually opening up the Adreno the development of documentation, of course, there have WP7 The reunification of the Qualcomm platform, Microsoft influence that is extreme to the force. Can be predicted that Qualcomm platform game optimization more and more to the force, and high-pass version of the game there have been many.
the MSM 7230/MSM 8225 (45NM the L1 64KB L2 640KB support 768M DDR2) is a high-pass upgrade U, similar to the Ti OMAP 3630, but core upgrade than Ti kind display, built-in Adreno 205 show accelerated core. As to adhere to the Ti U-performance good, can go take a look at the Desire Z and the test scores of the MS 2, 800M MSM 7230 has been dry turn 1G the OMAP 3630, not to mention the Desire HD and mytouch 4G 1G of MSM 8225, this lobby. Other contemporaries, Ti, U support RAM is always so poor, that supports only up to 512 M OMAP 36X0 will not be Android 3.0 era and MS the OMAP 3430 Egg pain.
Finally above the graphics chip processing capacity:
the SGX 530 polygons to generate a rate of 14 million polygons / second, pixel fill rate 125 million / sec (since the OMAP frequency of 3430 of the SGX 530 down to 110M), so MS processing capacity of 7.7 million pixel fill rate of 68.75 million / sec.
Adreno 200 polygons to generate a rate of 22 million polygons / second, pixel fill rate 130 million / sec.
the SGX 535 polygons to generate a rate of 28 million polygons / sec Pixel Fill Rate 125 million / sec.
the SGX 540 polygons to generate a rate of 28 million polygons / second, pixel fill rate of 250 million / sec.
Adreno 205 polygon generation rate of 41 million polygons / second, pixel fill rate of 245 million / sec.
because the current phone although has been hard acceleration core, but no memory (heat and power can not control) the need to share the system RAM, so heavily dependent on the speed of RAM, which is also why MS overclocking pulled at the same time show the fraction of the core, using the same graphics core, Milestone2 to power than the MS because DDR2 Milestone2 (another Milestone2 of the SGX 530 revert to the default frequency of 200Mhz).
the way to handheld contrast, PSP polygon generation rate of 33 million polygons / second, pixel fill rate 664 million / sec. (PSP integrated 4M RERAM super cache memory, so games, cell phones can not be compared).
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global multimedia and communications chips the manufacturers ImaginationTechnologies technology companies, has recently (December 2010) announced the launch of its high-performance graphics core POWERVR SGX554, fully multi-processor silicon intellectual property (IP) will be available for the embedded design and mobile applications. POWERVR SGX554 products
can be set into a high-performance eight-pipeline single-core or multiprocessor (MP: multiprocessor) is set to 2 to 16 cores (16 to 28 pipelines) .
The introduction of the POWERVR SGX554 Department Imagination Company the POWERVR Series5XT Series family of products, new members, whose mission is to bring a higher level of the realm for mobile and embedded graphics applications.
SGX554 provides full support for DirectX 9 FeatureLevel functional level of ability, and this has a maximum hardware accelerated performance, making this product very suitable for use in tablet computers, computing devices, as well as smart phones and other fields. The SGX554 not only the heritage of the POWERVR SGX core of all the features and benefits, but also created the industry attention every square cm of performance (performance per mm2) and the new indicators of performance per milliwatt (performance per mW).
the company marketing vice president Tony King-Smith pointed out: “The new members of the the POWERVR Series5XT series silicon intellectual property core embedded graphics capabilities to provide a new level of SGX554 will allow those upgrade to a more expansive realm of embedded applications in power consumption and cost obsessively through our impeccable API (APIs) will be able to reach a cross-platform support, whether it is a variety of common embedded operating system or desktop operating system. Incidentally, we have in DX9 level of product for shipping up to three years, shipments can be said is one million to calculate the SGX554 will continue to use the DX9 driver in the past has been for the program. client firms can not only enjoy higher performance, but also can save a lot of development on the troubled. “
< br /> In addition, SGX554 also provides is already a consensus of the industry of desktop product marketing OpenGL 2.1 (including the integration of DRI2, EXA, and an support DRM X11), the OpenGL ES 1.1 and 2.0, the OpenVG 1.1 and OpenCL 1.1 Embedded the Profile embedded specifications for today any action or embedded core, this product has the most extensive API support.
As for the software, the software stack (software stacks) of The POWERVR the SGX has been adopted stringent Khronos and Microsoft follow the test (conformance tests), to ensure that the product development process can be quickly launched, and inclusive and able to swim in a wide range of embedded and desktop operating system environment. Whether it is a Linux, Android, MeeGo, the Palm WebOS, Nokia Maemo and Symbian, Windows Mobile, the Samsung Bada, and even today other operating system software settings, can POWERVR SGX highlight its powerful features.
This product is part of the the the POWERVR SGXSeries5XT graphics processor unit (GPU: Graphics Processing Unit) silicon intellectual property core family, the demands of its functionality is built in the past has been with the Series5 architecture on the significant performance and very successful this also long been applied in many fields of the SGX silicon intellectual property core family. All Series5XT the SGX core legislation based on second-generation general-purpose class rendering engine (USSE2: second-generation Universal ScalableShader Engine)
Series5 USSE than the previous generation rendering engine will provide more significant processing throughput capacity, but also have more architecture extends the ability, whether it is a single core or class of multiprocessing (MP) solutions, both to meet the low-power two-dimensional and three-dimensional (2D , 3D), and even general purpose (GP-GPUs), graphics processing requirements.
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cards Learn the Tegra2 of the Geforce ULP and the SGX Series5 basic characteristics of architecture, and these structures iPad iPad2 and Xoom three basic 3D performance test, I believe that everyone of these two The basic 3D performance and features of the architecture has been a general concept.
the current exploration and discovery program, in addition to in-depth the Geforce ULP and the SGX Series5 architecture details, and understand their weaknesses and shortcomings, and other mobile devices for 3D and flash performance-sensitive applications to discuss the also the basis of these details in-depth discussion behind on their more core issues, for example – with iPad2 release, we are not is to step into a more alarming than the special effects quality bottomless trap?
tied your seat belts, and believe me, which in turn is a brainstorming reading tour.
I can get flash hardware solution … what?
Flash has a small footprint, because the characteristics of object-oriented programming, great ease of use and extensive browser support, so it is widely used in the online player, embedded web advertising as well as the field of animation. Extensive use of Flash animation in the modern web, sometimes on a page may appear more than a dozen large and small Flash window.
Flash extensive use of the Vector (vector data), image processing, the computing power of the hardware, especially the vector throughput capacity oppression. online video sites acfun or bilibili of playing video allows the Flash to load the player comments, “barrage” effect to achieve synchronization with the video playback, such vector operations to the ultimate Flash application will often desktop The computer CPU, and even the I7 are “crazy out”, no wonder there is a good thing the players will be a lot of intensive barrage bilibili video as a means of testing CPU performance.
This vector performance of the squeeze even on the desktop platform, general-purpose processors have been unbearable if it to require constant attention to the power problem had to sacrifice the performance of SoC CPU , it can be said is simply an impossible task. Placed in front of the phone and tablet PC, the only option is to abandon the principle of universal, vector operations task to a specialized unit.
the Tegra2 the soft underbelly
Tegra2 mobile phones and tablet PCs just when most interest to users is the Tablet PC Flash hardware acceleration performance. Announced details of the architecture from NVIDIA, Tegra2 with hardware acceleration of Flash, heterogeneous design Geforce ULP traditional desktop Geforce framework of the ROP unit disassembly, isolated from a separate programmable mixing unit a lot of PBU ( programmable Blend, Unit), to complete the hardware Flash acceleration. Andrews system is running JAVA Dalvik virtual machine environment, NVIDIA even using JAVA the Dalvik innate multi-threading advantage opened up a separate thread for the Flash application, so the Geforce ULP heterogeneous architecture can better work with the CPU, and give full play to the parallel < br />
However, in the application process, most users found the use of Tegra2 of mobile phones and Tablet PC products have not reached the NVIDIA official claimed that the smooth hard Xie Flash level pressure Tegra2 platform for mobile phones in some cases seems to be the perfect smooth playback even the bilibili barrage level have the Flash application, but most of the time using the Tegra2 the mobile phones and tablet PCs in the face of more than Flash applications more or less there will drag frames, which are not smooth. Why is this?
The answer is not complicated – Flash player 10 processors need to support neon instruction set.
neon the instruction set is the ARM architecture under a set of SIMD floating-point instruction set, mainly for Vector instructions in parallel throughput and accelerate the implementation of simple neon is the SSE instruction set of the ARM CPU. Adobe and NVIDIA announced the details of the Flash hardware acceleration require the CPU to the Vector instruction throughput and resolution, after the completion of coding, filters, objects and materials to determine the basic style of processing in order to be processed by the Geforce ULP. If there is no acceleration of the neon instruction set, ARM CPU to complete the above instructions in the form of the pure general-purpose processing throughput is not only extremely slow, and will greatly increase the power consumption of the system.
Unfortunately, the the Tegra2 framework Cortex A9 processor, forget the neon instruction set with me.

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June 7, 2010
iPhone Simulator, = Intel
iPhone = the ARM difference between great, the Intel processor mainly for IA and IA-32, commonly known as x86. desktop processors (Celeron, Pentium, Core, etc.) and a series of server processors Zhiqiang (Xeon); IA-64 Intel independent development of 64 processors, only for Itanium (Itanium), and follow-up products Itanium 2, for high-end server market.
ARM architecture and IA architecture is essentially different. Here we simply compare the different IA32 and ARM architecture.
IA-32 processor is based on CISC architecture, the ARM is the representative of the RISC. RISC instruction set than CISC instruction set has the following characteristics:
simple instruction set – RISC instruction set provides only very limited operation, basically single-cycle execution of each instruction, the instruction length also fixed.
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2Load-Store, structure – in the RISC, the CPU will not have the data memory, all calculations are required to register. Register and memory communications from a single instruction to complete. In the CSIC, the CPU is directly memory operations.
more registers – and CISC, RISC-based processor, more general-purpose registers can be used, each register for data storage or addressing.
applications, the Intel IA-32 and IA-64 architecture processor for personal computers and servers, the ARM processor used in the embedded field.
iphone vs. gphone
Android to run Java programs. Java programs that run within the JAVA virtual machine. Android emulator running Android apk file;
iPhone Simulator to run x86 machine code, the iPhone a real machine running on an ARM machine code. ARM machine code program is not running on x86 machines, the iPhone simulator.
have a program source code can only be compiled in the iPhone Simulator x86 machine code and ARM machine code to run the iPhone Simulator and iPhone real machine.
of CISC vs. RISC-difference:
By Armin Gerritsen
– Which one is better? –
RISC vs of CISC is a topic quite popular on the Net. Everytime Intel (CISC) or Apple (RISC) introduces a new CPU, the topic pops up again. But what are CISC and RISC exactly, and is one of them really better?
This article tries to explain in simple terms what RISC and CISC are and what the future might bring for the both of them. This article is by no means intended as an article pro-RISC or pro-CISC. You draw your own conclusions …
CISC
Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC use CPU based on this architecture. For instance Intel and AMD CPU are based on CISC architectures.
Typically CISC chips have a large amount of different and complex instructions. The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instructionset, which provides programmers with assembly instructions to do a lot with short programs.
In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions.

RISC
Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions. Apple for instance uses RISC chips.
Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task.
An other advantage of RISC is that – in theory – because of the more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce.
Finally, it easier to write powerful optimised compilers, since fewer instructions exist.
RISC vs CISC
There is still considerable controversy among experts about which architecture is better. Some say that RISC is cheaper and faster and therefor the architecture of the future.
Others note that by making the hardware simpler, RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks.
Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper anyway.
RISC has now existed more than 10 years and hasn been able to kick CISC out of the market. If we forget about the embedded market and mainly look at the market for PC , workstations and servers I guess a least 75% of the processors are based on the CISC architecture. Most of them the x86 standard (Intel, AMD, etc.), but even in the mainframe territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay …
Is RISC than really not better? The answer isn quite that simple. RISC and CISC architectures are becoming more and more alike. Many of today RISC chips support just as many instructions as yesterday CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. Further more today CISC chips use many techniques formerly associated with RISC chips.
So simply said: RISC and CISC are growing to each other.
x86
An important factor is also that the x86 standard , as used by for instance Intel and AMD, is based on CISC architecture. X86 is thé standard for home based PC . Windows 95 and 98 won run at any other platform. Therefore companies like AMD an Intel will not abandoning the x86 market just overnight even if RISC was more powerful.
Changing their chips in such a way that on the outside they stay compatible with the CISC x86 standard, but use a RISC architecture inside is difficult and gives all kinds of overhead which could undo all the possible gains. Nevertheless Intel and AMD are doing this more or less with their current CPU . Most acceleration mechanisms available to RISC CPUs are now available to the x86 CPU as well.
Since in the x86 the competition is killing, prices are low, even lower than for most RISC CPU . Although RISC prices are dropping also a, for instance, SUN UltraSPARC is still more expensive than an equal performing PII workstation is.
Equal that is in terms of integer performance. In the floating point-area RISC still holds the crown. However CISC 7th generation x86 chips like the K7 will catch up with that.
The one exception to this might be the Alpha EV-6. Those machines are overall about twice as fast as the fastest x86 CPU available. However this Alpha chip costs about € 20000, not something you e willing to pay for a home PC. < br />
Maybe interesting to mention is that it no coincidence that AMD K7 is developed in co-operation with Alpha and is for al large part based on the same Alpha EV-6 technology.

EPIC
The biggest threat for CISC and RISC might not be eachother, but a new technology called EPIC. EPIC stands for Explicitly Parallel Instruction Computing. Like the word parallel already says EPIC can do many instruction executions in parallel to one another.
EPIC is a created by Intel and is in a way a combination of both CISC and RISC. This will in theory allow the processing of Windows-based as well as UNIX-based applications by the same CPU.
It will not be until 2000 before we can see an EPIC chip. Intel is working on it under code-name Merced. Microsoft is already developing their Win64 standard for it. Like the name says, Merced will be a 64-bit chip.
If Intel EPIC architecture is successful, it might be the biggest thread for RISC. All of the big CPU manufactures but Sun and Motorola are now selling x86 -based products, and some are just waiting for Merced to come out (HP, SGI). Because of the x86 market it is not likely that CISC will die soon, but RISC may.
So the future might bring EPIC processors and more CISC processors, while the RISC processors are becoming extinct.
Conclusion
The difference between RISC and CISC chips is getting smaller and smaller. What counts is how fast a chip can execute the instructions it is given and how well it runs existing software. Today, both RISC and CISC manufacturers are doing everything to get an edge on the competition.
The future might not bring victory to one of them, but makes both extinct. EPIC might make first RISC obsolete and later CISC too.
Written by AAGerritsen
for the CPU Site
March 9

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Three, according to the processor instruction execution earlier in the mid-points of the processor architecture, the following re-introduce in January 24th, 2011 by processing cracking cracking instruction execution mode split standards. Have already introduced to the server processor instruction execution are mainly these types of RISC, CISC, the VLIW and EPIC. It was also normalized for the VLIW Intel EPIC.
1, CISC architecture server
of CISC English full name of “Complex InstructionSet the Computer”, “complex instruction set computer”. Since the birth of the PC processor in the previous 32 CISC instruction set.
in the CISC microprocessor, the program instructions are executed sequentially serial, the various operations in each instruction is also a serial execution order. The order of execution of the advantages of simple control, but the utilization of the various parts of the machine, slow execution speed. Unequal length the instruction of this instruction set, instruction, programming and design processor is a bit trickier. Very common but has been based on the CISC instruction architecture system design software, microprocessor manufacturers have been taking CISC road of development, including Intel, AMD, there are other vendors has been renamed, such as Texas Instruments, Cyrix, and now 32 ago, the VIA and other processors. The server processor, CISC architecture server CPU Intel 32 and previous Xeon (Xeon) the P III , P II processors, AMD series.
2, RISC-based servers
RISC English full name of the the Reduced InstructionSet Computing, Chinese called “reduced instruction set computing. Some CISC machines tests showed that the frequency of use of a variety of instructions is a considerable disparity between the most commonly used is relatively simple instructions, they accounted for only 20% of the total number of instructions, but the frequency in the program accounted for 80% . Complex instruction set is bound to increase the complexity of the microprocessor, the microprocessor developed a long time, the high cost. Complex instructions require complex operation, which reduces the speed of the machine. The late 1970s, John Cocke proposed the idea of ??RISC. The early 1980s, Stanford University developed the MIPS machine, played an important role in the birth and development of the system computer (RISC) for the reduced instruction set. RISC microprocessors not only streamlined instruction set, superscalar and super pipeline architecture, greatly enhancing the parallel processing capabilities. 1987 Sun Microsystems, Inc. SPARC chips is the amount of the structure of a superscalar RISC processor. SGI introduced the MIPS processor, super-pipelined architecture, the RISC processor in a multiprocessor build parallel RISC systems plays a central role.
simple instruction of the RISC processor, a hardwired control logic, processing ability, speed, and the vast majority of UNIX workstation and server manufacturers in the world are used as RISC chip CPU. Such as the former DEC Alpha 21364, IBM Power PC G4, HP PA-8900, SGI R12000A and SUN Microsystems Ultra the SPARC II of RISC chip operating frequency is generally low, less power consumption and temperature rise is less, the machine less prone to failure and aging, and improve the reliability of the system. If SGI R12000A microprocessor depends mainly on the improvement of the microprocessor architecture to improve the overall performance of the processor, to run the application faster. Present, high-end servers, the vast majority of the success of the RISC instruction set, RISC microprocessor instruction set to simplify the assembly line and frequently used commands are available to hardware implementation, a large number of registers, so that most of the instruction operations between registers, improve processing speed. On the other hand is a RISC instruction set three cache – main memory – external memory storage structure, take the number of deposit and the number of instructions to be implemented separately, so that the processor can complete as many jobs, and not from the memory access information and slow down the processing speed.
3, VLIW architecture server
the VLIW English full name “a Very LongInstruction Word”, the Chinese called VLIW word, it is the U.S. Multiflow and Cydrome architecture designed in the 1980s, mainly used in Trimedia (Transmeta) Crusoe and Efficeon series processors. The latest AMD Athlon 64 processor series also uses the instruction set, including its server processor version of the Operon. EPIC (in the same Intel IA-64 architecture, a clear parallel instruction computing, detailed below) is also isolated from the VLIW instruction system.
the VLIW instruction set of words using the advanced design of the EPIC, 20 instruction per clock cycle can be run, the CISC typically run only 1-3 instructions, RISC-4 instructions, visible VLIW than CISC and RISC much more powerful. The biggest advantage of VLIW is to simplify the structure of the processor, delete the many complex control circuitry inside the processor, these circuits usually must be used in the superscalar chip (CISC and RISC) to coordinate work in parallel, VLIW all such work to the compiler to complete. VLIW has a simple structure, can also make the chip manufacturing cost reduction, low cost, energy consumption, much higher performance than the superscalar chip. VLIW is the latest way to simplify the processor, the VLIW chip does not require excessive amount of chips in the run-time coordination must be used when the parallel execution of complex control circuits. But many of these burden to the compiler to assume. But the word based on the VLIW instruction set CPU chip allows the program to become very large, and require more memory. More importantly, the compiler must be smarter, and the impact of the negative impact of a poor VLIW compiler performance than a poor RISC or CISC compiler.
4, EPIC,
the EPIC is a clear parallel instruction computing “is abbreviated, it is the most important ideas is the” parallel processing “. The processor must be dynamic analysis code to determine the best execution path. The use of parallel technology, the EPIC processor allows the compiler in advance to complete the sort of code, the code has made it clear a good arrangement, direct execution can be. For this reason, the EPIC processor must be able to parallel processing of large amounts of data. This processor requires multiple instruction pipelines, generally require more than one register, a wide data path as well as other specialized techniques (such as data pre-installed, etc.), ensure that the code can run smoothly, to avoid causing bottlenecks due to the processor. Obviously, EPIC, the biggest advantages is its efficiency. Efficiency is also largely depends on the compiler, EPIC processor whenever the can will give full play to their abilities to complete a meaningful expression, rather than passive waiting for instructions, or wait for the pipeline refresh. In addition, due to the instruction concluded that the data pre-installed, as well as explicit parallelism, but also significantly reduced the error of the branch prediction, because most of the code prior to execution to organize. Itanium and Itanium 2, Intel IA-64 architecture processor with this instruction technology. However, this instruction architecture classified as VLIW type, because it is isolated from the VLIW.
count processor based on EPIC parallel processing with previous IA-32 architecture, parallel processing is not the same. Continuous machine code generated by the compiler, and hardware to interpret the machine code and to do parallel processing of instruction. However, because the hardware can not fully determine the timing of parallel processing of instructions, so we also need some other techniques to optimize parallel processing; application of these technologies to a certain extent to enhance the ability of parallel processing, but also had a some, such as interrupted instruction stream, and other issues. More effectively to provide feedback data to the microprocessor, the Intel and Hewlett-Packard Company to jointly develop the EPIC technology, improved co-ordination between the processor and the application.
IA-32 architecture processors by the compiler to produce a continuous machine code, and then to interpret the machine code and hardware to do parallel processing of instruction. However, because the hardware can not fully determine the timing of parallel processing of instructions, so we also need some other techniques to optimize parallel processing; application of these technologies to a certain extent to enhance the ability of parallel processing, but also had a some, such as interrupt instruction data flow.
IA-64 EPIC instruction set is effective to solve this problem. With the EPIC technology, and the compiler to ensure the parallel processing of instructions can be more effective. EPIC compiler first analyzes the source code to determine which commands can do parallel processing, optimized the code, then generates the appropriate machine code. In fact, by the compiler to tell the microprocessor which commands to do parallel processing, rather than procedures consume the time of the microprocessor.